View W9412G6JH_4461567.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W9412G6JH 2 m ? ? publication release date: nov. 2 9 , 2011 - 1 - revision a03 table of contents - 1. general description ................................ ................................ ................................ ......... 4 2. features ................................ ................................ ................................ ................................ . 4 3. key parameters ................................ ................................ ................................ ................... 5 4. pin configuration ................................ ................................ ................................ ............... 6 5. pin description ................................ ................................ ................................ ..................... 7 6. block diagram ................................ ................................ ................................ ...................... 8 7. functional description ................................ ................................ ................................ .... 9 7.1 power up sequence ................................ ................................ ................................ ....... 9 7.2 command function ................................ ................................ ................................ ...... 10 7.2.1 bank activate command ................................ ................................ ........... 10 7.2. 2 bank precharge command ................................ ................................ ........ 10 7.2.3 precharge all command ................................ ................................ ............ 10 7.2.4 write command ................................ ................................ ......................... 10 7.2.5 write with auto - precharge command ................................ ........................ 10 7.2.6 read command ................................ ................................ ......................... 10 7.2.7 read with auto - precharge command ................................ ....................... 10 7.2.8 mode register set command ................................ ................................ .... 11 7.2.9 extended mode register set command ................................ ................... 11 7.2.10 no - operation command ................................ ................................ ............ 11 7.2.11 burst read stop command ................................ ................................ ....... 11 7.2.12 device deselect command ................................ ................................ ....... 11 7.2.13 auto refresh command ................................ ................................ ............ 11 7.2.14 self refresh entry command ................................ ................................ .... 12 7.2.15 self refresh exit command ................................ ................................ ....... 12 7.2.16 data write enable /disable command ................................ ...................... 12 7.3 read operation ................................ ................................ ................................ ............. 12 7.4 write operation ................................ ................................ ................................ ............. 13 7.5 precharge ................................ ................................ ................................ ..................... 13 7.6 burst termination ................................ ................................ ................................ ......... 13 7.7 refresh operation ................................ ................................ ................................ ........ 13 7.8 power down mode ................................ ................................ ................................ ....... 14 7.9 input clock frequency change during precharge power down mode ........................ 14 7.10 mode register operation ................................ ................................ .............................. 14
W9412G6JH publication release date: nov. 2 9 , 2011 - 2 - revision a03 7.10.1 burst length field (a2 to a0) ................................ ................................ ...... 14 7.10.2 addressing mode select (a3) ................................ ................................ .... 15 7.10.3 cas latency field (a6 to a4) ................................ ................................ ..... 16 7.10.4 dll reset bit (a8) ................................ ................................ ..................... 16 7.10.5 mode register/extended mode register change bits (ba0, ba1) .............. 16 7.10.6 extended mode register field ................................ ................................ .... 16 7.10.7 reserved field ................................ ................................ ............................ 16 8. operation mode ................................ ................................ ................................ ................. 17 8.1 simplified truth table ................................ ................................ ................................ ... 17 8.2 fu nction truth table ................................ ................................ ................................ ..... 18 8.3 function truth table for cke ................................ ................................ ....................... 21 8.4 simplified stated diagram ................................ ................................ ............................ 22 9. electrical characteristics ................................ ................................ ......................... 23 9.1 absolute maximum ratings ................................ ................................ .......................... 23 9.2 recommended dc operating conditions ................................ ................................ .... 23 9.3 capacitance ................................ ................................ ................................ .................. 24 9.4 leakage and output buffer characteristics ................................ ................................ .. 24 9.5 dc characteristics ................................ ................................ ................................ ........ 25 9.6 ac cha racteristics and operating condition ................................ ................................ 26 9.7 ac test conditions ................................ ................................ ................................ ....... 27 10. system characteristics for ddr sdram ................................ ................................ . 30 10.1 table 1: input slew rate for dq, dqs, and dm ................................ .......................... 30 10.2 table 2: input setup & hold time derating for slew rate ................................ ........... 30 10.3 table 3: input/output setup & hold time derating for slew rate ............................... 30 10.4 table 4: input/output setup & hold derating for rise/fall delta slew rate ................ 30 10.5 table 5: output slew rate characteristics (x16 devices only) ................................ ... 30 10.6 table 6: output slew rate matching ratio characteristics ................................ ......... 31 10.7 table 7: ac overshoot/undershoot specification for address and control pins ......... 31 10.8 table 8: overshoot/undershoot specification for data, strobe, and mask pins .......... 32 10.9 system notes: ................................ ................................ ................................ ............... 33 11. timing waveforms ................................ ................................ ................................ ............. 35 11.1 command input timing ................................ ................................ ................................ 35 11.2 t iming of the clk signals ................................ ................................ ............................ 35 11.3 read timing (burst length = 4) ................................ ................................ ................... 36 11.4 write timing (burst length = 4) ................................ ................................ .................... 37 11.5 dm, data mask (W9412G6JH) ................................ ................................ ................. 38 11.6 mode register set (mrs) timing ................................ ................................ ................. 39
W9412G6JH publication release date: nov. 2 9 , 2011 - 3 - revision a03 11.7 extend mode register set (emrs) timing ................................ ................................ .. 40 11.8 auto - precharge timing (read cycle, cl = 2) ................................ .............................. 41 11.9 auto - precharge timing (read cycle, cl = 2), continued ................................ ............. 42 11.10 auto - precharge timing (write cycle) ................................ ................................ .......... 43 11.11 read interrupted by read (cl = 2, bl = 2, 4, 8) ................................ ........................ 44 11.12 burst read stop (bl = 8) ................................ ................................ ............................ 44 11 .13 read interrupted by write & bst (bl = 8) ................................ ................................ .. 45 11.14 read interrupted by precharge (bl = 8) ................................ ................................ ..... 45 11.15 write interrupted by write (bl = 2, 4, 8) ................................ ................................ ..... 46 11.16 write interrupted by read (cl = 2, bl = 8) ................................ ................................ 46 11.17 write interrupted by read (cl = 3, bl = 4) ................................ ................................ 47 11.18 write interrupted by precharge (bl = 8) ................................ ................................ ..... 47 11.19 2 bank interleave read operation (cl = 2, bl = 2) ................................ ................... 48 11.20 2 bank interleave read operation (cl = 2, bl = 4) ................................ ................... 48 11.21 4 bank interleave read operation (cl = 2, bl = 2) ................................ ................... 49 11.22 4 bank interleave read operation (cl = 2, bl = 4) ................................ ................... 49 11.23 auto refresh cycle ................................ ................................ ................................ ..... 50 11.24 precharged/active power down mode entry and exit timing ................................ .... 50 11.25 input clock frequency change during precharge power down mode timing .......... 50 11.26 self refresh entry and exit timing ................................ ................................ ............. 51 12. package specification ................................ ................................ ................................ ............... 52 12.1 tsop (type ii) 66 l 400 mil ................................ ................................ ......................... 52 13. revision history ................................ ................................ ................................ ................ 53
W9412G6JH publication release date: nov. 2 9 , 2011 - 4 - revision a03 1. general description W9412G6JH is a cmo s double data rate synchronous dynamic random access memory (ddr sdram) ; organized as 2m words ? 4 banks ? 16 bits. W9412G6JH delivers a data bandwidth of up to 500 m words per second ( - 4 ). to fully comply with the personal computer industrial standard, w94 12g6jh is sorted into the following speed grades : - 4 , - 5 , - 5i , - 5k and - 6i . the - 4 is compliant to the ddr 5 00/cl3 and cl4 specification. the - 5 / - 5 i / - 5k grade parts are compliant to the ddr400/cl3 specification (the - 5 i industrial grade parts is guaranteed to support - 40c t a 85c , the - 5k automotive grade parts is guaranteed to support - 40c t a 10 5c ) . the - 6i grade parts is compliant to the ddr333/cl2.5 specification which is guaranteed to support - 40c t a 85c . all input reference to the positive edge of clk (except for dq, dm and cke). the timing reference point for the differential clock is when the clk and signals cross during a transition. write and read data are synchronized with the bo th edges of dqs (data strobe). by having a programmable mode register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9412G6JH is ideal for main memory in high performance applications. 2. features ? 2.5v ? 0.2v power supply for ddr400 /333 ? 2.4v~2.7v power supply for ddr 500 ? up to 2 50 mhz clock frequency ? double data rate architecture; two data transfers per clock cycle ? differential clock inputs (clk and ) ? dqs is edge - aligned with data for read; center - aligned with data for write ? cas latency: 2 , 2.5 , 3 and 4 ? burst length: 2, 4 and 8 ? auto refresh and self refresh ? precharged power down and active power down ? write data mask ? write latency = 1 ? 15.6s refresh interval (4 k/64 ms r efr esh ) , @ 0 c t a 85 c ? 3 . 9 s refresh interval (4 k/ 16 ms r efresh ) , @ 85 c < t a 10 5 c ? maximum burst refresh cycle: 8 ? interface: sstl _ 2 ? packaged in tsop ii 66 - pin , using lead free materials with rohs compliant note : n ot support self refresh function with t a > 85 c clk
W9412G6JH publication release date: nov. 2 9 , 2011 - 5 - revision a03 3. key parameter s sym bol description m in./ m ax. - 4 - 5/ - 5i / - 5k - 6i t ck clock cycle time cl = 2 min. - 7.5 ns 7.5 ns max. - 12 ns 12 ns cl = 2.5 min. - 6 ns 6 ns max. - 12 ns 12 ns cl = 3 min. 4 ns 5 ns 6 ns max. 12 ns 12 ns 12 ns cl = 4 min. 4 ns - - max. 12 ns - - t ras active to precharge command period min. 40 ns 4 0 ns 4 2 ns t rc active to ref/active command period min. 48 ns 50 ns 54 ns i dd 0 operating current: one bank active - precharge max. 6 0 ma 55 ma 50 ma i dd1 operating current: one bank active - read - precharge max. 75 ma 65 ma 5 5 ma i dd4 r burst operation read current max. 140 ma 120 ma 1 1 0 ma i dd4 w burst operation write current max. 135 ma 115 ma 100 ma i dd 5 auto refresh c urrent m ax . 75 ma 70 ma 65 ma i dd6 self refresh current max. 2 ma 2 ma 2 ma
W9412G6JH publication release date: nov. 2 9 , 2011 - 6 - revision a03 4. pin configuration v ss dq 15 v ss q dq 14 dq 13 v dd q dq 12 dq 11 v ss q dq 10 dq 9 v dd q dq 8 v ss nc udqs clk cke a 11 a 9 a 8 a 7 a 6 a 5 a 4 v ss 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v dd dq 0 v dd q dq 1 dq 2 v ss q dq 3 dq 4 v dd q dq 5 dq 6 v ss q dq 7 nc v dd q ba 0 ba 1 a 10 / ap a 0 a 1 a 2 a 3 cs ras cas we 28 29 30 31 32 33 39 38 37 36 35 34 v dd ldm nc ldqs nc v dd nc v ss q nc nc nc clk udm v ref
W9412G6JH publication release date: nov. 2 9 , 2011 - 7 - revision a03 5. pin description pin number pin name function description 28 ? 32, 35 ? 4 1 a0 ? a1 1 address multiplexed p ins for row and column address. row address: a0 ? a1 1 . column address: a0 ? a8. (a10 is used for auto - precharge) 26, 27 ba0, ba1 bank select select bank to activate during row address latch time, or bank to read/write during column address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 dq0 ? dq15 data input/ output the dq0 C dq 15 input and output data are synchronized with both edges of dqs. 16,51 ldqs, udqs data strobe dqs is bi - directional signal. dqs is input signal during write operation and output signal during read operation. it is edge - aligned with read data, center - aligned with write data. 24 chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. 23, 22, 21 , , command inputs command inputs (along with ) define the command being entered. 20, 47 ldm, udm write mask when dm is asserted high in burst write, the input data is masked. dm is synchronized with both edges of dqs. 45, 46 clk, differential clock inputs all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of . 44 cke clo ck enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. 49 v ref reference voltage v ref i s reference voltage for inputs. 1, 18, 33 v dd power power for logic circuit inside ddr sdram. 34, 48, 66 v ss ground ground for logic circuit inside ddr sdram. 3, 9, 15, 55, 61 v ddq power for i/o buffer separated power from v dd , used for output buffer, to improve noise. 6, 12, 52, 58, 64 v ssq ground for i/o buffer separated ground from v ss , used for output buffer, to improve noise. 14, 17, 19, 25, 42, 43, 50, 53 nc no connection no connection cs ras cas we clk
W9412G6JH publication release date: nov. 2 9 , 2011 - 8 - revision a03 6. block diagram cke a 10 dll clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank # 2 column decoder sense amplifier cell array bank # 0 column decoder sense amplifier cell array bank # 3 data control circuit dq buffer column decoder sense amplifier cell array bank # 1 note : the cell array configuration is 4096 * 512 * 16 r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r a 0 a 9 a 11 ba 1 ba 0 cs ras cas we clk clk dq 0 dq 15 prefetch register ldm udm udqs ldqs
W9412G6JH publication release date: nov. 2 9 , 2011 - 9 - revision a03 7. functional descripti on 7.1 power up sequence (1) apply power and attempt to cke at a low state ( 0.2v), all other inputs may be undefined 1) apply v dd before or at the same time as v ddq . 2) apply v ddq before or at the same time as v tt and v ref . (2) start clock and maintain stable condition for 200 s (min.). (3) after stable power and clock, apply nop and take cke high. (4) issue precharge command for all banks of the device. (5) issue emrs (extended mode register set) to enable dll and establish output driver type. (6) issue mrs (mode register set) to reset dll and set device to idle with bit a8. (an ad ditional 200 cycles(min) of clock are required for dll lock before any executable command applied.) (7) issue precharge command for all banks of the device. (8) issue two or more auto refresh commands. (9) issue mrs - initialize device operation with the reset dll bit d eactivated a8 to low. initialization sequence after power - up ? 2 clock min . t rfc mrs clk command any cmd aref aref prea mrs emrs prea clk t rfc t rp t rp enable dll dll reset with a 8 = high disable dll reset with a 8 = low 200 clock min . 2 clock min . 2 clock min . inputs m aintain stable for 200 s min .
W9412G6JH publication release date: nov. 2 9 , 2011 - 10 - revision a03 7.2 command function 7.2.1 bank activate command ( = l, = h, = h, ba0, ba1 = bank, a0 to a1 1 = row address) the bank activate command activates the bank designated by the ba (bank address) signal. row addresses are latched on a0 to a1 1 when this command is issued and the cell data is read out of the sense amplifiers. the maximum time that each ba nk can be held in the active state is specified as t ras (max) . after this command is issued, read or write operation can be executed. 7.2.2 bank precharge command ( = l, = h, = l, ba0, ba1 = bank, a10 = l, a0 to a9, a11 = dont care) the bank precharge command percharges the bank designated by ba. the precharged bank is switched from the active state to the idle state. 7.2.3 precharge all command ( = l, = h, = l, ba0, ba1 = dont care, a10 = h, a0 to a9, a11 = dont care) the precharge all command precharges all banks simultaneously. then all banks are switched to the idle state. 7.2.4 write command ( = h, = l, = l, ba0, ba1 = bank, a10 = l, a0 to a8 = column address) the write command performs a write operation to the bank designated by ba. the write data are latched at both edges of dqs. the leng th of the write data (burst length) and column access sequence (addressing mode) must be in the mode register at power - up prior to the write operation. 7.2.5 write with auto - precharge command ( = h, = l, = l, ba0, ba1 = bank, a10 = h, a0 to a8 = column address) the write with auto - precharge command performs the precharge operation automatically after the write operation. this command must not be interrupted by any other commands. 7.2.6 read command ( = h, = l, = h, ba0, ba1 = bank, a10 = l, a0 to a8 = column address) the read command performs a read operation to the bank designated by ba. the read data are synchr onized with both edges of dqs. the length of read data (burst length), addressing mode and cas latency (access time from command in a clock cycle) must be programmed in the mode register at power - up prior to the read operation. 7.2.7 read with auto - precharge command ( = h, = l, = h, ba0, ba1 = bank, a10 = h, a0 to a8 = column address) the read with auto - precharge command automatically performs the precharge operation after the read operation. ras cas we
W9412G6JH publication release date: nov. 2 9 , 2011 - 11 - revision a03 1) reada t ras (min) - (bl/2) x t ck internal precharge operation begins after bl/2 cycle from read with auto - p recharge command. 2) t rcd(min) reada < t ras(min) - (bl/2) x t ck data can be read w ith shortest latency, but the internal precharge operation does not begin until after t ras (min) has completed. this command must not be interrupted by any other command. 7.2.8 mode register set command ( = l, = l , = l, ba0 = l, ba1 = l, a0 to a1 1 = register data) the mode register set command programs the values of cas l atency, addressing mode, burst length and dll reset in the mode register. the default values in the mode register aft er power - up are undefined, therefore this command must be issued during the power - up sequence. also, this command can be issued while all banks are in the idle state. refer to the table for specific codes. 7.2.9 extended mode register set command ( = l, = l, = l, ba0 = h, ba1 = l, a0 to a1 1 = register data) the extended mode register set command can be implemented as needed for function extensions to the standard (sdr - sdram). currently the only available mode in emrs is dll enable/disable, decoded by a0. the default value of the extended mode register is not defined; therefore this command must be issued during the power - up sequence for enabling dll. refer to the table for specific codes . 7.2.10 no - operation command ( = h, = h, = h) the no - operation command simply performs no operation (same command as device deselect). 7.2.11 burst read stop command ( = h, = h, = l) the burst stop command is used to stop the burst operation. this command is only valid during a burst read operation. 7.2.12 device deselect command ( = h) the device deselec t command disables the command decoder so that the , , and address inputs are ignored. this command is similar to the no - operation command. 7.2.13 auto refresh command ( = l, = l, = h, cke = h , ba0, ba1, a0 to a1 1 = dont care) auto refresh is used during normal operation of the ddr sdram and is analogous to cas C before C ras (cbr) refresh in previous dram types. this co mmand is non persistent, so it must be issued e ach time a refresh is required. the r e fresh addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto refresh command. the ddr sdram requires auto cs ? ras cas we ?
W9412G6JH publication release date: nov. 2 9 , 2011 - 12 - revision a03 refr esh cycles at an average periodic interval of t refi (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given ddr sdram, and the max i mum absolute interval between any auto refresh command and the next auto refresh command is 8 * t refi . 7.2.14 self refresh entry command ( = l, = l, = h , cke = l, ba0, ba1, a0 to a1 1 = dont care) the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the se lf refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh. any time the dll is enabled a dll reset must fo llow and 200 clock cycles should occur before a read command can be issued. input signals except cke are dont care during self refresh. since cke is a sstl_2 input, v ref must be maintained during self refresh . 7.2.15 self refresh exit command (cke = h, = h or cke = h, = h, = h) the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable prior to cke going back high. once cke is high, the ddr sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command. the use of self refreh mode introduces the possibility that an internally timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended . 7.2.16 data write enable /di sable command (dm = l/h or ldm, udm = l/h) during a write cycle, the dm or ldm, udm signal functions as data mask and can control every word of the input data. the ldm signal controls dq0 to dq7 and udm signal controls dq8 to dq15. 7.3 read operation issui ng the bank activate command to the idle bank puts it into the active state. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially, synchronized with both edges of dqs (burst read operation). the initi al read data becomes available after cas l atency from the issuing of the read command. the cas l atency must be set in the mode register at power - up. when the precharge operation is performed on a bank during a burst read and operation, the burst operation is terminated. when the read with auto - precharge command is issued, the precharge operation is performed automatically after the read cycle then the bank is switched to the idle state. this command cannot be interrupted by any other commands. refer to the diagrams for read operation. cs ras cas we
W9412G6JH publication release date: nov. 2 9 , 2011 - 13 - revision a03 7.4 write operation issuing the write command after t rcd from the bank activate command. the input data is latched sequentially, synchronizing with both edges(rising & falling) of dqs after the write command (burst write operation) . the burst length of the write data (burst length) and addressing mode must be set in the mode register at power - up. when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated. when the write with auto - precharge command is issued, the precharge operation is performed automatically after the write cycle, then the bank is switched to the idle state, the write with auto - precharge command cannot be interrupted by any other command for the entire burst data duration. refer to the diagrams for write operation. 7.5 precharge there are two commands, which perform the precharge operation (bank precharge and precharge all). when the bank precharge command is issued to the active bank, the bank is precharged and t hen switched to the idle state. the bank precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. the maximum time each bank can be held in the active state is specified as t ras (max) . the refore, each bank must be precharged within t ras (max) from the bank activate command. the precharge all command can be used to precharge all banks simultaneously. even if banks are not in the active state, the precharge all command can still be issued. in this case, the precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. 7.6 burst termination when the precharge command is used for a bank in a burst cycle, the burst operation is terminated. when bu rst read cycle is interrupted by the precharge command, read operation is disabled after clock cycle of ( cas l atency) from the precharge command. when the burst write cycle is interrupted by the precharge command , the input circuit is reset at the same clo ck cycle at which the precharge command is issued. in this case, the dm signal must be asserted high during t wr to prevent writing the invalided data to the cell array. when the burst read stop command is issued for the bank in a burst read cycle, the bu rst read operation is terminated. the burst read stop command is not supported during a write burst operation. refer to the diagrams for burst termination. 7.7 refresh operation two types of refresh operation can be performed on the device: auto refresh and se lf refresh. by repeating the auto refresh cycle, each bank in turn refreshed automatically. the refresh operation must be performed 4096 times (rows) within 64m s . the period between the auto refresh command and the next command is specified by t rfc . self refresh mode enter s issuing the self refresh command (cke asserted low) w hile all banks are in the idle state. the device is in self refresh mode for as long as cke held low. in the case of distributed auto refresh commands, distributed auto refresh co mmands must be issued every 15.6 s and the last distributed auto refresh commands must be performed within 15.6 s before entering the self refresh mode. after exiting from the self refresh mode, the refresh operation must be performed within 15.6 s. in self refresh mode, all input/output buffers are disable d ,
W9412G6JH publication release date: nov. 2 9 , 2011 - 14 - revision a03 resulting in lower power dissipation (except cke buffer). refer to the diagrams for refresh operation. 7.8 power down mode two types of power down mode can be performed on the device: active standby pow er down mode and precharge standby power down mode. when the device enters the power down mode, all input/output buffers are disabled resulting in low power dissipation (except cke buffer). power down mode enter asserting cke low while the device is not running a burst cycle. taking cke high can exit this mode. when cke goes high, a no operation command must be input at next clk rising edge. refer to the diagrams for power down mode. 7.9 input clock frequency change during precharge power down mode ddr sdra m input clock frequency can be changed under following condition: ddr sdram must be in precharged power down mode with cke at logic low level. after a minimum of 2 clocks after cke goes low, the clock frequency may change to any frequency between minimum a nd maximum operating frequency specified for the particular speed grade. during an input clock frequency change, cke must be held low. once the input clock frequency is changed, a stable clock must be provided to dram before precharge power down mode may b e exited. the dll must be reset via emrs after precharge power down exit. an additional mrs command may need to be issued to appropriately set cl etc. after the dll relock time, the dram is ready to operate with new clock frequency. 7.10 mode register operation the mode register is programmed by the mode register set command (mrs/emrs) when all banks are in the idle state. the data to be set in the mode register is transferred using the a0 to a1 1 and ba0, ba1 address inputs. the mode register designates the oper ation mode for the read or write cycle. the register is divided into five filed: (1) burst length field to set the length of burst data (2) addressing mode selected bit to designate the column access sequence in a burst cycle (3) cas latency field to set t he assess time in clock cycle (4) dll reset field to reset the dll (5) regular/extended mode register filed to select a type of mrs (regular/extended mrs). emrs cycle can be implemented the extended function (dll enable/disable mode). the initial value of the mode register (including emrs) after power up is undefined; therefore the mode register set command must be issued before power operation. 7.10.1 burst length field (a2 to a0) this field specifies the data length for column access using the a2 to a0 pins and sets the burst length to be 2, 4 and 8 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x reserved
W9412G6JH publication release date: nov. 2 9 , 2011 - 15 - revision a03 7.10.2 addressing mode select (a3) the addressing mode can be one of two modes; interleave mode or sequential mode, when the a3 bit is 0, sequential mode is selected. when the a3 bit is 1, interleave mode is selected. both addressing mode support burst length 2, 4 and 8 words. a3 addressing mode 0 sequential 1 interleave 7.10.2.1. addressing sequence of sequential mode a column access is performed by incrementing the column address input to the device. the address is varied by the burst length as the following. addressing sequence of sequential mode d ata access address burst length data 0 n 2 words (address bits is a0) data 1 n + 1 not carried from a0 to a1 data 2 n + 2 4 words (address bit a0, a1) data 3 n + 3 not carried from a1 to a2 data 4 n + 4 data 5 n + 5 8 words (address bits a2, a1 and a0) data 6 n + 6 not carried from a2 to a3 data 7 n + 7 7.10.2.2. address ing sequence for interleave mode a column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence of interleave mode d ata access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words data 1 a8 a7 a6 a5 a4 a3 a2 a1 data 2 a8 a7 a6 a5 a4 a3 a2 a0 4 words data 3 a8 a7 a6 a5 a4 a3 a2 data 4 a8 a7 a6 a5 a4 a3 a1 a0 8 words data 5 a8 a7 a6 a5 a4 a3 a1 data 6 a8 a7 a6 a5 a4 a3 a0 data 7 a8 a7 a6 a5 a4 a3 a0 a1 a2 a2
W9412G6JH publication release date: nov. 2 9 , 2011 - 16 - revision a03 7.10.3 cas latency field (a6 to a4) this field specifies the number of clock cycles from the assertion of the read command to the first data read. the minimum values of cas latency depend on the frequency of clk. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 reserved 1 1 0 2.5 1 1 1 reserved 7.10.4 dll reset bit (a8) this bit is used to reset dll. when the a8 bit is 1, dll is reset. 7.10.5 mode register/extended mode register change bits (ba0, ba1) these bits are used to select mrs/emrs. ba1 ba0 a1 1 - a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1 x reserved 7.10.6 extended mode register field 1) dll switch field (a0) this bit is used to select dll enable or disable a0 dll 0 enable 1 disable 2) output driver strength control field ( a6, a1) the 100%, 60% and 30% or matched impedance driver strength are required extended mode register set (emrs) as the following: a 6 a1 buffer strength 0 0 100% strength 0 1 60% strength 1 0 reserved 1 1 3 0% strength 7.10.7 reserved field ? test mode entry bit (a7) this bit is used to enter test mode and must be set to 0 for normal operation. ? reserved bits (a9, a10, a11) these bits are reserved for future operations. they must be set to 0 for normal operation.
W9412G6JH publication release date: nov. 2 9 , 2011 - 17 - revision a03 8. operation mode the following table shows the operation commands. 8.1 simplified truth table s ym . c ommand d evice s tate cken - 1 cken dm (4) ba0, ba1 a10 a 0 - a9 , a 11 act bank active idle (3) h x x v v v l l h h pre bank precharge any (3) h x x v l x l l h l prea precharge all any h x x x h x l l h l writ write active (3) h x x v l v l h l l writa write with auto - precharge active (3) h x x v h v l h l l read read active (3) h x x v l v l h l h reada read with auto - precharge active (3) h x x v h v l h l h mrs mode register set idle h x x l, l c c l l l l emrs extended mode register set idle h x x h, l v v l l l l nop no operation any h x x x x x l h h h bst burst read stop active h x x x x x l h h l dsl device deselect any h x x x x x h x x x aref auto refresh idle h h x x x x l l l h self self refresh entry idle h l x x x x l l l h selex self refresh exit idle (self refresh) l h x x x x h x x x l h h x pd power down m ode entry idle/ active (5) h l x x x x h x x x l h h x pdex power down mode exit any (power down) l h x x x x h x x x l h h x wde data write enable active h x l x x x x x x x wdd data write disable active h x h x x x x x x x notes ? 1. v = valid x = dont care l = low level h = high level 2. cke n signal is input level when commands are issued. cke n - 1 signal is input level one clock cycle before the commands are issued. 3 . these are state designated by the ba0, ba1 signals. 4 . ldm, udm ( W9412G6JH ) . 5 . power down mode can not entry in the burst cycle. cs ras cas we
W9412G6JH publication release date: nov. 2 9 , 2011 - 18 - revision a03 8.2 function truth table (note 1) c urrent s tate a ddress c ommand a ction notes idle h x x x x dsl nop l h h x x nop/bst nop l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act row activating l l h l ba, a10 pre/prea nop l l l h x aref/self refresh or self refresh 2 l l l l op - code mrs/emrs mode register accessing 2 row active h x x x x dsl nop l h h x x nop/bst nop l h l h ba, ca, a10 read/reada begin read: determine ap 4 l h l l ba, ca, a10 writ/writa begin write: determine ap 4 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea precharge 5 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal read h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst burst stop l h l h ba, ca, a10 read/reada term burst, new read: determine ap 6 l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea term burst, p recharging l l l h x aref/self illegal l l l l op - code mrs/emrs illegal write h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada term burst, start read: determine ap 6, 7 l h l l ba, ca, a10 writ/writa term burst, start read: determine ap 6 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea term burst , precharging 8 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal cs ras cas we
W9412G6JH publication release date: nov. 2 9 , 2011 - 19 - revision a03 function truth table, continued c urrent s tate a ddress c ommand a ction notes read with auto - p recha r ge h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal l l l h x aref/self illegal l l l l op - code mrs/emrs illegal write with auto - precharge h x x x x dsl continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal precharging h x x x x dsl nop - > idle after t rp l h h h x nop nop - > idle after t rp l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea idle after t rp l l l h x aref/self illegal l l l l op - code mrs/emrs illegal row activating h x x x x dsl nop - > row active after t rcd l h h h x nop nop - > row active after t rcd l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal cs ras cas we
W9412G6JH publication release date: nov. 2 9 , 2011 - 20 - revision a03 function truth table, continued c urrent s tate a ddress c ommand a ction notes write recovering h x x x x dsl nop - > row active after t wr l h h h x nop nop - > row active after t wr l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal write recovering with auto - precharge h x x x x dsl nop - > enter precharge after t wr l h h h x nop nop - > enter precharge after t wr l h h l x bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/prea illegal 3 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal refreshing h x x x x dsl nop - > idle after t rc l h h h x nop nop - > idle after t rc l h h l x bst illegal l h l h x read/writ illegal l l h x x act/pre/prea illegal l l l x x aref/self/mrs/emrs illegal mode register accessing h x x x x dsl nop - > row after t mrd l h h h x nop nop - > row after t mrd l h h l x bst illegal l h l x x read/writ illegal l l x x x act/pre/prea/are f/self/mrs/emrs illegal notes ? 1. all entries assume that cke was active (high level) during the preceding clock cycle and the current clock cycle. 2. illegal if any bank is not idle. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. illegal if t rcd is not satisfied. 5. illegal if t ras is not satisfied. 6. must sat isfy burst interrupt condition. 7. must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. must mask preceding data which dont satisfy t wr remark: h = high level, l = low level, x = high or low level (dont care), v = valid da ta cs ras cas we
W9412G6JH publication release date: nov. 2 9 , 2011 - 21 - revision a03 8.3 function truth table for cke current state cke address action notes n - 1 n self refresh h x x x x x x invalid l h h x x x x exit self refresh - > idle after t xsnr l h l h h x x exit self refresh - > idle after t xsnr l h l h l x x illegal l h l l x x x illegal l l x x x x x maintain self refresh power down h x x x x x x invalid l h x x x x x exit power down - > idle after t is l l x x x x x maintain power down mode all banks idle h h x x x x x refer to function truth table h l h x x x x enter power down 2 h l l h h x x enter power down 2 h l l l l h x self refresh 1 h l l h l x x illegal h l l l x x x illegal l x x x x x x power down row active h h x x x x x refer to function truth table h l h x x x x enter power down 3 h l l h h x x enter power down 3 h l l l l h x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x power down any state other than listed above h h x x x x x refer to function truth table notes ? 1. self refresh can enter only from the all banks idle state. 2. p ower d own occurs when all banks are idle; this mode is referred to as precharge power down. 3. p ower d own occurs when there is a row active in any bank ; this mode is referred to as active power down. remark: h = high level, l = low level, x = high or low level (dont care), v = valid data cs ras cas we
W9412G6JH publication release date: nov. 2 9 , 2011 - 22 - revision a03 8.4 s implified s tated d iagram power applied automatic sequence command sequence read a write read row act ive power down idle mode regist er set aut o refresh self refresh read read a write write a pre charge power on mrs/emrs aref sref srefx pd pdex act bst read write write a write a read a pre pre pre pre act ive powerdown pd pdex read read a
W9412G6JH publication release date: nov. 2 9 , 2011 - 23 - revision a03 9. electrical characteristics 9.1 a bsolute m aximum r atings p arameter s ymbol r ating u nit voltage on any pin relative to v ss v in, v out - 0. 5 ~ v ddq + 0. 5 v voltage on v dd /v dd q supply relative to v ss v dd, v ddq - 1 ~ 3.6 v operating temperature ( - 4/ - 5) t opr 0 ~ 70 c operating temperature ( - 5i/ - 6i) t opr - 40 ~ 85 c operating temperature ( - 5k) t opr - 40 ~ 105 c storage temperature t stg - 55 ~ 150 c soldering temperature (10s) t solder 260 c power dissipation p d 1 w short circuit output current i out 50 ma note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated i n the operational sections of this specification is not implied. exposure to absolute maximum rating conditi ons for extended periods may affect reliability. 9.2 r ecommended dc o perating c onditions ( t a = 0 to 70 c for - 4/ - 5 , t a = - 40 to 85 c for - 5i/ - 6 i , t a = - 40 to 105 c for - 5k ) s ym. p arameter m in . t yp . m ax . u nit n otes v dd power supply voltage (for - 5 / - 5i/ - 5k/ - 6i ) 2.3 2.5 2.7 v 2 v dd power supply voltage (for - 4 ) 2. 4 - 2. 7 v 2 v ddq i/o buffer supply voltage ( for - 5/ - 5i/ - 5k/ - 6i ) 2.3 2.5 2.7 v 2 v ddq i/o buffer supply voltage (for - 4 ) 2. 4 - 2. 7 v 2 v ref input reference voltage 0.49 x v ddq 0.50 x v ddq 0.51 x v ddq v 2, 3 v tt termination voltage (system) v ref - 0.04 v ref v ref + 0.04 v 2, 8 v ih (dc) input high voltage (dc) v ref + 0.15 - v ddq + 0.3 v 2 v il (dc) input low voltage (dc) - 0.3 - v ref - 0.15 v 2 v ick (dc) differential clock dc input voltage - 0.3 - v ddq + 0.3 v 15 v id (dc) input differential voltage. clk and inputs (dc) 0.36 - v ddq + 0.6 v 13, 15 v ih (ac) input high voltage (ac) v ref + 0.31 - - v 2 v il (ac) input low voltage (ac) - - v ref - 0.31 v 2 v id (ac) input differential voltage. clk and inputs (ac) 0.7 - v ddq + 0.6 v 13, 15 v x (ac) differential ac input cross point voltage v ddq /2 - 0.2 - v ddq /2 + 0.2 v 12, 15 v iso (ac) differential clock ac middle point v ddq /2 - 0.2 - v ddq /2 + 0.2 v 14, 15 notes : v ih (dc) and v il (dc) are levels to maintain the current logic state . v ih (ac) and v il (ac) are levels to change to the new logic state. clk
W9412G6JH publication release date: nov. 2 9 , 2011 - 24 - revision a03 9.3 c apacitance (v dd = v ddq = 2.5v ? 0.2v, f = 1 mhz, t a = 25 c , v out (dc) = v ddq /2, v out (peak to peak) = 0.2v) s ymbol p arameter m in . m ax . d elta (m ax .) u nit c in input capacitance (except for clk pins) 2.0 4 .0 0.5 pf c clk input capacitance (clk pins) 3 .0 5 .0 0.25 pf c i/o dq, dqs, dm capacitance 1 . 5 5. 5 0.5 pf c nc nc pin capacitance - 1.5 - pf notes: these parameters are periodically sampled and not 100% tested. the nc pins have additional capacitance for adjustment of the adjacent pin capacitance. 9.4 l eakage and o utput b uffer c haracteristic s s ymbol p arameter m in . m ax . u nit n otes i i (l) input leakage current any input 0v < v in < v dd , v ref pin 0v < v in < 1.35v ( all other pins not under test = 0v) - 2 2 a i o (l) output leakage current (output disabled, 0v < v out < v ddq ) - 5 5 a v oh output high voltage (under ac test load condition) v tt +0.76 - v v ol output low voltage (under ac test load condition) - v tt - 0.76 v i oh output levels: full drive option h igh c urrent (v out = v ddq - 0.373v, m in . v ref , min . v tt - 15 - ma 4, 6 i ol low c urrent (v out = 0.373v, max . v ref , m ax . v tt ) 15 - ma 4, 6 i oh r output levels: reduced drive option - 6 0% h igh c urrent (v out = v ddq - 0. 76 3v, m in . v ref , min . v tt - 9 - ma 5 i ol r low c urrent (v out = 0. 76 3v, max . vref, m ax . v tt ) 9 - ma 5 i ohr (30) output levels: reduced drive option - 30 % h igh c urrent (v out = v ddq C 1.056 v, m in . v ref , min . v tt - 4.5 - ma 5 i o l r (30) low c urrent (v out = 1.056 v, max . v ref , m ax . v tt ) 4.5 - ma 5
W9412G6JH publication release date: nov. 2 9 , 2011 - 25 - revision a03 9.5 dc c haracteristic s s ym . p arameter max. u nit n otes - 4 - 5/ - 5i/ - 5k - 6i i dd0 o perating current : one bank active - precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every tw o clock cycle s. 60 55 5 0 ma 7 i dd1 o perating current : one bank active - read - precharge; burst = 4 ; t rc = t rc min; cl = 3 ; t ck = t ck min; i out = 0 ma; address and control inputs changing once per clock cycle . 75 65 55 7, 9 i dd2p precharge power down standby curren t : all banks idle; power down mode; cke < v il max; t ck = t ck min; vin = v ref for dq, dqs and dm . 5 5 5 i dd2n i dle standby current : > v ih min; all banks idle; cke > v ih min; t ck = t ck min; address and other control inputs changing once per clock cycle; vin > v ih min or vin < v il max for dq, dqs and dm . 2 5 20 20 7 i dd3p a ctive power down standby current : one bank active; power down mode; cke < v il max; t ck = t ck min ; vin = v ref for dq, dqs and dm . 15 1 0 1 0 i dd3n active standby current : > v ih min; cke > v ih min; one bank active - precharge; t rc = t ras max; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle . 35 30 3 0 7 i dd4r operating current : burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl= 2 ; t ck = t ck min; i out = 0ma . 1 40 1 2 0 1 1 0 7, 9 i dd4w operating current : burst = 2; write; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2 ; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle . 1 3 5 1 15 1 0 0 7 i dd5 auto refresh current : t rc = t rfc min . 75 7 0 65 7 i dd6 self refresh current : cke < 0.2v; external clock on ; t ck = t ck min . 2 2 2 i dd7 r andom r ead current : 4 banks active read with activate every 20n s , auto - precharge read every 20 ns; burst = 4; t rcd = 3; i out = 0ma; dq, dm and dqs inputs changing twice per clock cycle; address changing once per clock cycle . 17 0 15 0 13 0 cs
W9412G6JH publication release date: nov. 2 9 , 2011 - 26 - revision a03 9.6 ac c haracteristics and o perating c onditio n s ym . p arameter - 4 - 5/ - 5i / - 5k - 6i u nit n otes m in . m ax . m in . m ax . m in . m ax . t rc active to ref/active command period 48 50 54 ns t rfc ref to ref/active command period 60 70 70 t ras active to precharge command period 4 0 7 0000 4 0 7 0000 4 2 1 0 0000 t rcd active to read/write command delay time 16 15 18 t rap active to read with auto - precharge enable 16 15 18 t ccd read/write(a) to read/write(b) command period 1 1 1 t ck t rp precharge to active command period 16 15 18 ns t rrd active(a) to active(b) command period 12 1 0 1 2 t wr write recovery time 12 1 5 15 t dal auto - precharge write recovery + precharge time (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) (t wr /t ck ) + (t rp /t ck ) t ck 18 t ck clk cycle time cl = 2 - - 7.5 1 2 7.5 1 2 ns cl = 2.5 - - 6 1 2 6 1 2 cl = 3 4 12 5 1 2 6 1 2 cl = 4 4 12 - - - - t ac data access time from clk, - 0. 65 0. 65 - 0.7 0.7 - 0.7 0.7 16 t dqsck dqs output access time from clk, - 0. 55 0. 55 - 0.6 0.6 - 0.6 0.6 t dqsq data strobe edge to output data edge skew 0. 4 0.4 0. 4 t ch clk high level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 11 t cl clk low level width 0.45 0.55 0.45 0.55 0.45 0.55 t hp clk half period (minimum of actual t ch, t cl ) min (t cl ,t ch ) m in, (t cl ,t ch ) m in, (t cl ,t ch ) ns t qh dq output data hold time from dqs t hp - 0.5 t hp - 0.5 t hp - 0.5 t rpre dqs read preamble time 0. 9 1.1 0.9 1.1 0.9 1.1 t ck 11 t rpst dqs read postamble time 0.4 0.6 0.4 0.6 0.4 0.6 t ds dq and dm setup time 0.4 0.4 0. 4 ns t dh dq and dm hold time 0.4 0.4 0. 4 t dipw dq and dm input pulse width (for each input) 1. 75 1.75 1.75 t dqsh dqs input high pulse width 0. 35 0. 35 0. 35 t ck 11 t dqsl dqs input low pulse width 0. 35 0. 35 0. 35 t dss dqs falling edge to clk setup time 0.2 0.2 0.2 t dsh dqs falling edge hold time from clk 0.2 0.2 0.2 t wpres clock to dqs write preamble set - up time 0 0 0 ns clk
W9412G6JH publication release date: nov. 2 9 , 2011 - 27 - revision a03 ac c haracteristics and o perating c ondition, continued s ym . p arameter - 4 - 5/ - 5i / - 5k - 6i u nit n otes m in . m ax . m in . m ax . m in . m ax . t wpre dqs write preamble time 0. 25 0. 25 0. 25 t ck 11 t wpst dqs write postamble time 0.4 0.6 0.4 0.6 0.4 0.6 t dqss write command to first dqs latching transition 0. 85 1. 15 0. 75 1. 25 0.75 1.25 t is input setup time (fast slew rate) 0. 6 0. 6 0. 75 ns 19, 21 - 23 t ih input hold time (fast slew rate) 0. 6 0. 6 0. 75 19, 21 - 23 t is input setup time (slow slew rate) 0. 7 0. 7 0. 8 20 - 23 t ih input hold time (slow slew rate) 0. 7 0. 7 0. 8 20 - 23 t ipw control & address input pulse width (for each input) 2.2 2.2 2.2 t hz data - out high - impedance time from clk, 0.7 0.7 0.7 t lz data - out low - impedance time from clk, - 0. 7 0. 7 - 0.7 0.7 - 0.7 0.7 t t(ss) sstl input transition 0.5 1.5 0.5 1.5 0.5 1.5 t wtr internal write to read command delay 2 2 1 t ck t xsnr exit self refresh to non - read command 7 2 7 5 75 n s t xsrd exit self refresh to read command 200 200 200 t ck t ref i refresh interval time ( 4 k/ 64ms ) 15.6 15.6 15.6 s 17 t ref ia refresh interval time ( 4k/16ms ) * - 3.9 - s 17 t mrd mode register set cycle time 8 1 0 1 2 ns * when - 5k speed grade operation at 85 c < t a 1 0 5 c , increasing 4k auto r efresh commands in frequency to a 16 ms period . 9.7 ac t est c onditions p arameter s ymbol v alue u nit input high voltage (ac) v ih v ref + 0.31 v input low voltage (ac) v il v ref - 0.31 v input reference voltage v ref 0.5 x v ddq v termination voltage v tt 0.5 x v ddq v differential clock input reference voltage v r v x (ac) v input difference voltage. clk and inputs (ac) v id (ac) 1.5 v output timing measurement reference voltage v otr 0.5 x v ddq v clk clk
W9412G6JH publication release date: nov. 2 9 , 2011 - 28 - revision a03 notes : (1) conditions outside the limits listed under absolute maximum ratings may cause permanent damage to the device . (2) all voltages are referenced to v dd , v dd q. (3) peak to peak ac noise on v ref may not exceed ? 2% v ref(dc). (4) v oh = 1.95v, v ol = 0.35v (5) v oh = 1.9v, v ol = 0.4v (6) the values of i oh(dc) is based on v ddq = 2.3v and v tt = 1.19v. the values of i ol(dc) is based on v ddq = 2.3v and v tt = 1.11v. (7) these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck and t rc . (8) v tt is not applied directly to the device. v tt is a system supply for signal termination resistor s is expected to be set equal to v ref and must track variatio ns in the dc level of v ref . (9) these parameters depend on the output loading. specified values are obtained with the output open. (10) transition times are measured between v ih min(ac) and v il max(ac) .transition (rise and fall) of input signals have a fixed slope. (11) if the result of nominal calculation with regard to t ck contains more than one decimal place, the result is rounded up to the nearest decimal place. ( i.e., t dqss = 1 . 2 5 ? t ck , t ck = 5 ns , 1 . 2 5 ? 5 ns = 6 .25 ns is rounded up to 6 . 2 ns .) (12) v x is the differential clock cross point voltage where input timing measurement is referenced. (13) v id is magnitude of the difference between clk input level and input level. (14) v iso means {v ick (clk)+v ick ( )}/2. (15) refer to the figure below. clk v s w i n g ( m a x ) v d d q v s s t t v i h m i n ( a c ) v r e f v i l m a x ( a c ) s l e w = ( v i h m i n ( a c ) - v i l m a x ( a c ) ) / t o u t p u t 5 0 v t t t i m i n g r e f e r e n c e l o a d o u t p u t v ( o u t ) 3 0 p f
W9412G6JH publication release date: nov. 2 9 , 2011 - 29 - revision a03 (16) t ac and t dqsck depend on the clock jitter. these timing are measured at stable clock. (17) a maximum of eight auto refresh commands can be posted to any given ddr sdram device. (18) t dal = (t wr /t ck ) + (t rp /t ck ) for each of the terms above, if not already an integer, round to the next highest integer. example: for - 5 speed grade at cl=2.5 and tck= 6 n s t dal = ((15 n s / 6 n s ) + ( 15 n s / 6 n s )) clocks = (( 3 ) + (3)) clocks = 6 clocks (19) for command/address input slew rate 1.0 v/n s . (20) for command/address input slew rate 0.5 v/n s and <1.0 v / ns. (21) for c l k & slew rate 1.0 v/n s (single -- ended). (22) these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. (23) slew rate is measured between v oh (ac) and v ol (ac) . clk clk v ss v ick v x v x v x v x v x v ick v ick v ick v id(ac) v i d(ac) 0 v differential v iso v iso(min) v iso(max) v ss clk
W9412G6JH publication release date: nov. 2 9 , 2011 - 30 - revision a03 10. system characteristi cs for ddr sdram the following specification parameters are required in systems using ddr 500 , ddr 400 & ddr 333 devices to ensure proper system performance. these characteristics are for system simulation pu rposes and are guaranteed by design . 10.1 table 1: input slew rate for dq, dqs, and dm ac characteristics s ymbol ddr 5 00 ddr400 ddr333 unit notes parameter min. max. min. max. min. max. dq/dm/dqs input slew rate measured between v ih(dc) , v il(dc) and v il(dc) , v ih(dc) dcslew 0.5 4.0 0.5 4.0 0.5 4.0 v/n s a, m 10.2 table 2: input setup & hold time derating for slew rate input slew rate t is t ih unit notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i 10.3 table 3: input/output setup & hold time derating for slew rate input slew rate t ds t dh unit notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 0 ps k 0.3 v/ns +150 0 ps k 10.4 table 4 : input/output setup & hold derating for rise/fall delta slew rate input slew rate t ds t dh unit notes ? 0.0 ns/v 0 0 ps j ? 0.25 ns/v +50 0 ps j ? 0.5 ns/v +100 0 ps j 10.5 table 5 : output slew rate characteristic s (x 16 devices only) slew rate characteristic typical range (v/n s ) minimum (v/n s ) maximum (v/n s ) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a, c, d, f, g, h pulldown slew rate 1.2 ~ 2.5 0.7 5.0 b , c, d, f, g, h
W9412G6JH publication release date: nov. 2 9 , 2011 - 31 - revision a03 10.6 table 6 : output slew rate matching ratio characteristics slew rate characteri stic ddr500 ddr400 ddr333 notes p arameter min. max. min. max. min. max. output slew rate matching ratio (pullup to pulldown) 0.67 1.5 0.67 1.5 0.67 1.5 e, m 10.7 table 7: ac overshoot/undershoot specification for address and control pins parameter specification ddr500 ddr400 ddr333 maximum peak amplitude allowed for overshoot 1.5 v 1.5 v 1.5 v maximum peak amplitude allowed for undershoot 1.5 v 1.5 v 1.5 v the area between the overshoot signal and vdd must be less than or equal to max. area in figure 3 4 . 5 v - ns 4 . 5 v - ns 4 . 5 v - ns the area between the undershoot signal and gnd must be less than or equal to max. area in figure 3 4 . 5 v - ns 4 . 5 v - ns 4 . 5 v - ns figure 3 : address and control ac overshoot and undershoot definition 0 0 . 5 0 . 6 8 7 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 6 . 0 6 . 3 1 2 5 6 . 5 7 . 0 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 m a x . a m p l i t u d e = 1 . 5 v o v e r s h o o t v d d m a x . a r e a m a x . a m p l i t u d e = 1 . 5 v g n d u n d e r s h o o t t i m e ( n s ) v o l t s ( v )
W9412G6JH publication release date: nov. 2 9 , 2011 - 32 - revision a03 10.8 table 8: overshoot/undershoot specification for data, strobe, and mask pin s parameter specification ddr500 ddr400 ddr333 maximum peak amplitude allowed for overshoot 1. 2 v 1. 2 v 1. 2 v maximum peak amplitude allowed for undershoot 1. 2 v 1. 2 v 1. 2 v the area between the overshoot signal and vdd must be less than or equal to max. area in figure 4 2.4 v - ns 2.4 v - ns 2. 4 v - ns the area between the undershoot signal and gnd must be less than or equal to max. area in figure 4 2.4 v - ns 2.4 v - ns 2. 4 v - ns figure 4 : dq/dm/dqs ac overshoot and undershoot definition 0 0 . 5 1 . 0 1 . 4 2 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 5 . 6 8 6 . 0 6 . 5 7 . 0 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 m a x . a m p l i t u d e = 1 . 2 v o v e r s h o o t v d d m a x . a r e a m a x . a m p l i t u d e = 1 . 2 v g n d u n d e r s h o o t t i m e ( n s ) v o l t s ( v )
W9412G6JH publication release date: nov. 2 9 , 2011 - 33 - revision a03 10.9 system notes: a. pullup slew rate is characterized under the test conditions as shown in figure 1 . figure 1 : pullup slew rate test load b. pulldown slew rate is measured under the test conditions shown in figure 2 . figure 2 : pulldown slew rate test load c. pullup slew rate is measured between ( v ddq /2 - 320 mv 250 mv ) pulldown slew rate is measured between ( v ddq /2 + 320 mv 250 mv ) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. example: for typical slew rate, dq0 is switching for minimum slew rate, all dq bits are switching worst case pattern for maximum slew rate , only one dq is switching fr om either high to low , or low to high the remaining dq bits remain the same as for previous state d. evaluation conditions typical: 25 o c (t ambient), v ddq = nominal, typical process minimum: 70 o c (t ambient), v ddq = minimum, slow - slow process maximum: 0 o c (t ambient), v ddq = maximum, fast - fast process v s s q 5 0 o u t p u t t e s t p o i n t v d d q 5 0 o u t p u t t e s t p o i n t
W9412G6JH publication release date: nov. 2 9 , 2011 - 34 - revision a03 e. the ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum differe nce between pullup and pulldown drivers due to process variation. f. verified under typical conditions for qualification purposes. g. tsop ii package devices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to increase t is and t ih in the case where the input slew rate is below 0.5 v/n s as shown in table 2 . the input slew rate is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , similarly for rising transitions. j. a derating factor will be used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ, as shown in tables 3 & 4 . input slew rate is based on the larger of ac - ac delta rise, fall rate and dc - dc delta rise, fall rate. input slew rate is based on the lesser of the slew rates determined by either v ih(ac) to v il(ac) or v ih(dc) to v il(dc) , similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example: if slew rate 1 is 0.5 v/n s a nd slew rate 2 is 0.4 v/n s , then the delta rise, fall rate is - 0.5 n s /v. using the table given, this would result in the need for an increase in t ds and t dh of 100 p s . k. table 3 is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/n s . the i/o slew rate is based on the lesser of the ac - ac slew rate and the dc - dc slew rate. the input slew rate is based on the lesser of the slew rates determined by either v ih( ac ) to v il(ac) or v ih(dc) to v il(dc) , and similarly for rising transitions. m. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic.
W9412G6JH publication release date: nov. 2 9 , 2011 - 35 - revision a03 11. timing waveforms 11.1 command input timing 11.2 timing of the clk signals c l k c l k t c k t c k t c l t c h t i s t i h t i s t i h t i s t i h t i s t i h t i s t i h c s r a s c a s w e a 0 ~ a 1 1 b a 0 , 1 r e f e r t o t h e c o m m a n d t r u t h t a b l e t c k t t t t v i h v i h ( a c ) v i l ( a c ) v i l c l k c l k c l k c l k v x v x v x v i h v i l t c h t c l
W9412G6JH publication release date: nov. 2 9 , 2011 - 36 - revision a03 11.3 read timing (burst length = 4) notes : the correspondence of ldqs, udqs to dq. ( W9412G6JH ) ldqs dq0~7 udqs dq8~15 t i s t i h d a 0 d a 1 d a 2 t c h t c l t c k a d d c m d c l k c l k r e a d c o l q a 0 q a 1 q a 2 d a 3 q a 3 t r p r e t d q s c k t d q s c k t d q s c k t r p s t p o s t a m b l e p r e a m b l e h i - z h i - z t d q s q t d q s q t d q s q t q h t q h t a c t l z t h z h i - z h i - z d a 0 d a 1 d a 2 q a 0 q a 1 q a 2 d a 3 q a 3 t r p r e t d q s c k t d q s c k t d q s c k t r p s t p o s t a m b l e p r e a m b l e h i - z h i - z t d q s q t d q s q t d q s q t q h t q h t a c t l z t h z h i - z h i - z c a s l a t e n c y = 2 d q s o u t p u t ( d a t a ) c a s l a t e n c y = 3 d q s o u t p u t ( d a t a ) t i s t i h
W9412G6JH publication release date: nov. 2 9 , 2011 - 37 - revision a03 11.4 write timing (burst length = 4) note: x16 has two dqs s (udqs for u p per byte and ldqs for lower byte). even if one of the 2 bytes is not used, both udqs and ldqs must be toggled. t i s t i h t d s h t d s s t d s s t d s h t w p r e s t d h t d h t d h t d s t d s t d s t d q s s t d s h t d s h t d s s t d s s p o s t a m b l e t w p r e p r e a m b l e t d q s h t d q s h t d q s l t w p s t d a 0 d a 1 d a 2 d a 3 t w p r e s t d s t d s t d q s s t d s h t d s h t d s s t d s s p o s t a m b l e t w p r e p r e a m b l e t d q s h t d q s h t d q s l t w p s t t w p r e s t d h t d s t d s t d q s s p o s t a m b l e t w p r e p r e a m b l e t d q s h t d q s h t d q s l t w p s t d a 0 d a 1 d a 2 d a 3 t d s t d h t d h t c h t c l t c k d q s i n p u t ( d a t a ) l d q s d q 0 ~ 7 u d q s d q 8 ~ 1 5 x 4 , x 8 d e v i c e x 1 6 d e v i c e a d d c m d c l k c l k w r i t c o l d a 0 d a 1 d a 2 d a 3 d a 0 d a 1 d a 2 d a 3 t d h t d h t d h t d s d a 0 d a 1 d a 2 d a 3 d a 0 d a 1 d a 2 d a 3 t i s t i h
W9412G6JH publication release date: nov. 2 9 , 2011 - 38 - revision a03 11.5 dm, data mask ( W9412G6JH ) w r i t t d i p w t d i p w t d h t d h t d s t d s m a s k e d c l k c m d l d q s l d m d q 0 ~ d q 7 d 3 d 1 d 0 t d i p w t d i p w t d h t d h t d s t d s m a s k e d u d q s u d m d q 8 ~ d q 1 5 d 3 d 2 d 0 c l k
W9412G6JH publication release date: nov. 2 9 , 2011 - 39 - revision a03 11.6 mode register set (mrs) timing mrs register set data next cmd t mrd clk clk cmd add a 2 a 1 a 0 a 3 a 6 a 5 a 4 a 8 ba 1 ba 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 1 1 0 0 0 1 0 1 2 4 8 2 4 8 burst length sequential interleaved reserved reserved reserved reserved reserved reserved sequential interleaved addressing mode cas latency 2 dll reset no yes mrs or emrs regular mrs cycle extended mrs cycle 2 . 5 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 ba 0 ba 1 " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " dll reset reserved addressing mode * " reserved " should stay " 0 " during mrs cycle . reserved mode register set or extended mode register set cas latency burst length reserved reserved 3 4
W9412G6JH publication release date: nov. 2 9 , 2011 - 40 - revision a03 11.7 extend mode register set (emrs) timing emrs register set data next cmd t mrd clk clk cmd add a 0 ba 1 ba 0 0 1 1 1 0 0 0 1 0 1 enable disable dll switch mrs or emrs regular mrs cycle extended mrs cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 ba 0 ba 1 " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " * " reserved " should stay " 0 " during emrs cycle . " 0 " " 0 " " 0 " " 0 " " 0 " " 0 " buffer strength dll switch reserved mode register set or extended mode register set reserved buffer strength a 1 buffer strength 100 % strength a 6 1 1 0 0 0 1 0 1 60 % strength 30 % strength reserved
W9412G6JH publication release date: nov. 2 9 , 2011 - 41 - revision a03 11.8 auto - precharge timing (read c ycle, cl = 2) 1) t rcd (reada) ? t ras (min) C (bl/2) ? t ck notes: cl = 2 shown; same command operation timing with cl = 2,5 and cl=3 in this case, the internal precharge operation begin after bl/2 cycle from reada command. represents the start of internal precharging. the read with au to - precharge command cannot be interrupted by any other command. a p q 7 q 6 q 5 q 4 q 3 q 2 q 1 q 0 a c t r e a d a a c t q 0 q 1 q 2 q 3 a c t r e a d a a c t q 0 q 1 a c t a p r e a d a a c t t r p t r a s c m d d q s d q c m d d q s d q c m d d q s d q b l = 2 b l = 4 b l = 8 c l k c l k a p ap
W9412G6JH publication release date: nov. 2 9 , 2011 - 42 - revision a03 11.9 auto - precharge timing (read cycle, cl = 2), continued 2 ) t rcd/rap(min) ? t rcd (reada) ? t ras (min) C (bl/2) ? t ck notes: cl2 shown; same command operation timing with cl = 2.5, cl=3. in this case, the internal precharge operation does not begin until after t ras (min) has command. represents the start of internal precharging. the read with auto - precharge command cannot be interrupted by any other command. ap a p q 7 q 6 q 5 q 4 q 3 q 2 q 1 q 0 a c t r e a d a a c t q 0 q 1 q 2 q 3 a c t r e a d a a c t q 0 q 1 a c t a p r e a d a a c t t r p t r a s c m d d q s d q c m d d q s d q c m d d q s d q b l = 2 b l = 4 b l = 8 c l k c l k a p t r a p t r c d t r a p t r c d t r a p t r c d
W9412G6JH publication release date: nov. 2 9 , 2011 - 43 - revision a03 11.10 auto - precharge timing (write cycle) the write with auto - precharge command cannot be interrupted by any other command. represents the start of internal precharging . ap a p a c t a c t w r i t a a c t w r i t a c m d d q s d q c m d d q s d q c m d d q s d q b l = 2 b l = 4 b l = 8 c l k c l k a p a p d 0 d 1 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t d a l t d a l t d a l w r i t a
W9412G6JH publication release date: nov. 2 9 , 2011 - 44 - revision a03 11.11 read interrupted by read (cl = 2, bl = 2, 4, 8) 11.12 burst read stop (bl = 8) c m d a d d d q s c l k c l k d q a c t r e a d a r e a d b r e a d c r e a d d r e a d e r o w a d d r e s s c o l , a d d , a c o l , a d d , b c o l , a d d , c c o l , a d d , d c o l , a d d , e q c 0 q a 0 q a 1 q b 0 q b 1 t c c d t c c d t c c d t c c d t r c d r e a d c m d d q s d q c l k c l k b s t q 0 q 1 q 2 q 3 q 4 q 5 q 0 q 1 q 2 q 3 q 4 q 5 c a s l a t e n c y c a s l a t e n c y c a s l a t e n c y = 2 d q s d q c a s l a t e n c y = 3
W9412G6JH publication release date: nov. 2 9 , 2011 - 45 - revision a03 11.13 read interrupted by write & bst (bl = 8) burst read cycle must be terminated by bst command to avoid i/o conflict. 11.14 read interrupted by precharge (bl = 8) r e a d c m d d q s d q c l k c l k b s t q 0 q 1 q 2 q 3 q 4 q 5 c a s l a t e n c y = 2 w r i t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 r e a d c m d d q s d q c l k c l k p r e q 0 q 1 q 2 q 3 q 4 q 5 q 0 q 1 q 2 q 3 q 4 q 5 c a s l a t e n c y c a s l a t e n c y c a s l a t e n c y = 2 d q s d q c a s l a t e n c y = 3
W9412G6JH publication release date: nov. 2 9 , 2011 - 46 - revision a03 11.15 write interrupted by write (bl = 2, 4, 8) 11.16 write interrupted by read (cl = 2, bl = 8) c m d a d d d q s c l k c l k d q a c t w r i t a w r i t b w r i t c w r i t d w r i t e r o w a d d r e s s c o l . a d d . a c o l . a d d . b c o l . a d d . c c o l . a d d . d c o l . a d d . e d c 0 d c 1 d d 0 d d 1 d a 0 d a 1 d b 0 d b 1 t c c d t c c d t c c d t c c d t r c d w r i t c m d d q s d m c l k c l k t w t r d q d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d a t a m u s t b e m a s k e d b y d m r e a d d a t a m a s k e d b y r e a d c o m m a n d , d q s i n p u t i g n o r e d . q 4 q 5 q 6 q 7 q 0 q 1 q 2 q 3
W9412G6JH publication release date: nov. 2 9 , 2011 - 47 - revision a03 11.17 write interrupted by read (cl = 3 , bl = 4) 11.18 write interrupted by precharge (bl = 8) w r i t c m d d q s d m c l k c l k r e a d t w t r d q q 0 q 1 q 2 q 3 d 0 d 1 d 2 d 3 d a t a m u s t b e m a s k e d b y d m w r i t c m d d q s d m c l k c l k a c t t w r d q d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d a t a m u s t b e m a s k e d b y d m p r e t r p d a t a m a s k e d b y p r e c o m m a n d , d q s i n p u t i g n o r e d .
W9412G6JH publication release date: nov. 2 9 , 2011 - 48 - revision a03 11.19 2 bank interleave read operation (cl = 2, bl = 2) 11.20 2 bank interleave read operation (cl = 2, bl = 4) c m d d q s c l k c l k d q q 0 a q 1 a q 0 b q 1 b a c t a / b : b a n k a c t . c m d o f b a n k a / b r e a d a a / b : r e a d w i t h a u t o p r e . c m d o f b a n k a / b a p a / b : a u t o p r e . o f b a n k a / b a c t a a c t b r e a d a a a c t a r e a d a b a c t b a p a a p b t r c d ( a ) t r a s ( a ) t r p ( a ) t r a s ( b ) t r c d ( b ) t r p ( b ) c l ( a ) c l ( b ) p r e a m b l e p o s t a m b l e p r e a m b l e p o s t a m b l e t r r d t r c ( a ) t r c ( b ) t r r d c m d d q s c l k c l k d q q 2 a q 3 a q 2 b q 3 b a c t a / b : b a n k a c t . c m d o f b a n k a / b r e a d a a / b : r e a d w i t h a u t o p r e . c m d o f b a n k a / b a p a / b : a u t o p r e . o f b a n k a / b a c t a r e a d a a a c t b r e a d a b a c t a a c t b a p a a p b t r c d ( a ) t r a s ( a ) t r p ( a ) t r a s ( b ) t r c d ( b ) t r p ( b ) c l ( a ) c l ( b ) p r e a m b l e p o s t a m b l e t r r d t r c ( a ) t r c ( b ) t r r d q 0 a q 1 a q 0 b q 1 b
W9412G6JH publication release date: nov. 2 9 , 2011 - 49 - revision a03 11.21 4 bank interleave read operation (cl = 2, bl = 2) 11.22 4 bank interleave read operation (cl = 2, bl = 4) c m d d q s c l k c l k d q q 0 a q 1 a q 0 b q 1 b a c t a / b / c / d : b a n k a c t . c m d o f b a n k a / b / c / d r e a d a a / b / c / d : r e a d w i t h a u t o p r e . c m d o f b a n k a / b / c / d a p a / b / c / d : a u t o p r e . o f b a n k a / b / c / d a c t a a c t b r e a d a a a c t c r e a d a b a c t d r e a d a c a c t a a p a a p b t r c d ( a ) t r a s ( a ) t r p t r a s ( b ) t r c d ( b ) c l ( a ) c l ( b ) p r e a m b l e p o s t a m b l e p r e a m b l e t r r d t r c ( a ) t r r d t r a s ( c ) t r a s ( d ) t r c d ( d ) t r c d ( c ) t r r d t r r d c m d d q s c l k c l k d q a c t a / b / c / d : b a n k a c t . c m d o f b a n k a / b / c / d r e a d a a / b / c / d : r e a d w i t h a u t o p r e . c m d o f b a n k a / b / c / d a p a / b / c / d : a u t o p r e . o f b a n k a / b / c / d a c t a r e a d a a a c t b r e a d a b a c t c r e a d a c a c t d r e a d a d a c t a a p a a p b t r c d ( a ) t r a s ( a ) t r p ( a ) t r a s ( b ) t r c d ( b ) c l ( a ) c l ( b ) t r r d t r c ( a ) t r r d t r a s ( c ) t r a s ( d ) t r c d ( d ) t r c d ( c ) t r r d t r r d q 2 a q 3 a q 2 b q 3 b p r e a m b l e q 0 a q 1 a q 0 b q 1 b q 0 a q 1 a c l ( c ) a p c
W9412G6JH publication release date: nov. 2 9 , 2011 - 50 - revision a03 11.23 auto refresh cycle note: cke has to be kept high level for auto - refresh cycle. 11.24 precharged/active power down mode entry and exit timing note: 1. if power down occurs when all banks are idle, this mode is referred to as precharge power down. 2. i f power down occurs when there is a row active in any bank, this mode is referred to as active power down . 11.25 input clock frequency change during precharge power down mode timing c m d c l k c l k p r e a a r e f a r e f c m d n o p n o p n o p t r p t r f c t r f c c m d c l k c l k n o p c m d n o p e x i t e n t r y c m d n o p t i h t i s t c k t i h t i s c k e p r e c h a r g e / a c t i v a t e n o t e 1 , 2 n o p n o p n o p d l l r e s e t n o p n o p c m d 2 0 0 c l o c k s t i s f r e q u e n c y c h a n g e o c c u r s h e r e m i n m u m 2 c l o c k s r e q u i r e d b e f o r e c h a n g i n g f r e q u e n c y s t a b l e n e w c l o c k b e f o r e p o w e r d o w n e x i t c l k c l k c m d c k e t r p
W9412G6JH publication release date: nov. 2 9 , 2011 - 51 - revision a03 11.26 self ref resh entry and exit timing note: if the clock frequency is changed during self refresh mode, a dll reset is required upon exit. c m d c l k c l k t i h t i s t i h t i s s e l f c m d s e l e x n o p n o p p r e a e x i t e n t r y c k e t r p t x s r d n o p s e l f t x s n r s e l f x n o p a c t r e a d n o p e x i t e n t r y
W9412G6JH publication release date: nov. 2 9 , 2011 - 52 - revision a03 12. package specificatio n 12.1 tsop (type ii) 66l 400 mil c o n t r o l l i n g d i m e n s i o n : m i l l i m e t e r s e 1 e b 1 3 3 6 6 3 4 e s e a t i n g p l a n e d a 2 a 1 a z d y d e t a i l a l r a d . r l 1 1 c r a d . r 1 d e t a i l a s y m b o l d i m e n s i o n ( m m ) m i n . n o m . m a x . a a 1 a 2 b c e e 1 d l 1 1 . 5 6 1 0 . 0 3 0 . 6 5 b a s i c 2 2 . 0 9 2 2 . 2 2 2 2 . 3 5 0 . 1 2 1 . 2 0 0 . 1 5 1 . 0 5 0 . 3 8 - - - 0 . 2 2 0 . 9 5 0 . 0 5 - - - 1 . 0 0 - - - - - - 0 . 4 0 e d i m e n s i o n ( i n c h ) m i n . n o m . m a x . 0 . 4 5 5 0 . 3 9 5 0 . 0 2 6 b a s i c 0 . 8 7 0 0 . 8 7 5 0 . 8 8 0 0 . 0 0 5 0 . 0 4 7 0 . 0 0 6 0 . 0 4 1 0 . 0 1 5 - - - 0 . 0 0 9 0 . 0 3 7 0 . 0 0 2 - - - 0 . 0 3 9 - - - - - - 0 . 0 1 6 1 1 . 7 6 1 1 . 9 6 1 0 . 1 6 1 0 . 2 9 0 . 0 0 8 - - - 0 . 4 6 3 0 . 4 7 1 0 . 4 0 0 0 . 4 0 5 0 . 5 0 0 . 6 0 0 . 0 2 0 0 . 0 2 4 0 . 8 0 b a s i c 0 . 0 3 1 b a s i c l 1 r r 1 0 . 2 5 - - - 0 . 1 2 - - - - - - 0 . 1 2 0 . 0 1 0 - - - 0 . 0 0 5 - - - - - - 0 . 0 0 5 0 . 7 1 r e f 0 . 0 2 8 r e f z d 1 y 8 2 0 0 . 1 0 - - - 1 0 - - - - - - - - - 0 8 2 0 0 . 0 0 4 - - - 1 0 - - - - - - - - - 0 0 . 2 1 - - -
W9412G6JH publication release date: nov. 2 9 , 2011 - 53 - revision a03 13. rev i sion history ver sion d ate p age d escription a01 apr. 0 2 , 2010 all initial f ormally data shee t a02 jul. 0 8 , 2011 4~5, 23, 25~27, 30~32 add - 5i and - 6i industrial grade part s a03 nov. 2 9 , 2011 4~5, 23, 25~27 add - 5 k a utomotive grade part s important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation ins truments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead t o a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

▲Up To Search▲

Price & Availability of W9412G6JH

	To Download W9412G6JH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .